1. Field of the Invention
The present invention relates to an integrated circuit comprising a resistive memory cell which can be switched between a highly resistive memory state and at least one lowly resistive memory state, and to a method of evaluating a memory state of a resistive memory cell. The invention further relates to a memory chip, an electronic device and a memory module.
2. Description of the Related Art
In various data processing systems and electronic devices, use is made of so-called non-volatile memory chips. These memories comprise programmable memory cells in which stored information is reliably maintained even without external power supply. Thereby, contrary to so-called volatile memories such as DRAMs (dynamic random access memory), no memory content is lost immediately upon switching off the supply voltage of the memory.
A type of non-volatile memory is the so-called flash memory. In this kind of memory, a single memory cell consists of a field effect transistor which comprises an isolated auxiliary electrode, called the “floating gate”, between the gate and the source/drain channel of the transistor. In order to program the flash memory cell, a high positive potential is applied to the gate, thereby depositing electrical charge (electrons) on the auxiliary electrode. The uncharged state of the auxiliary electrode is restored by expelling the charge from the auxiliary electrode by means of applying a high negative potential to the gate. The charge on the auxiliary electrode thereby affects the conductivity or the resistance of the source/drain channel of the switched-on transistor, respectively, which is used for setting the memory state of the flash memory cell.
Moreover, non-volatile resistive memories are known which are based on the utilization of further electrical properties and phenomena. An exemplary one of these is the CBRAM memory (conductive bridging RAM) in which a memory cell comprises a resistive memory element with an electrolyte material arranged between two electrodes, the electrolyte material having a high specific resistance. By applying a programming voltage to the electrodes, a conductive path may be produced in the electrolyte material, causing the resistive memory cell to be switched from a highly resistive state to a lowly resistive state. Changing from the highly resistive state to the lowly resistive state may be reversed by applying a corresponding erase voltage. The different resistances thereby define detectable memory states of the memory cell.
A further resistive memory is the so-called phase change memory, also called PCRAM. In this memory, a memory cell comprises a resistive memory element with a phase change material, typically a metal alloy, arranged between two electrodes. By means of electrical pulses, the phase change material is heated and thereby switched between an (initially) amorphous phase state and a crystalline phase state. Depending on the phase state, the resistive memory cell is thereby transferred into a highly resistive memory state (amorphous phase) and into a lowly resistive memory state (crystalline phase), which is used for storing information.
For reading out information from a memory cell of a CBRAM or a PCRAM memory chip, a predetermined read voltage may be applied to the memory cell by means of a read circuit in order to generate an electrical current flow through the memory cell. The strength of the electrical current thereby depends on the resistive state of the resistive memory cell. By detecting an electrical quantity depending on the current, typically a voltage drop at a load element serially connected to the memory cell, the memory state of the memory cell may be evaluated. For this purpose, the electrical quantity is compared to a reference quantity. The reference quantity is usually obtained depending on an electrical current caused by applying the predetermined read voltage to two parallel-connected resistive memory cells, which serve as reference cells. Thereby, one of these reference cells is in a highly resistive state whereas the other reference cell is in a lowly resistive state so that the parallel-connected reference cells reflect a reference state at two parallel-connected load elements with a resistance value between the highly resistive and the lowly resistive memory state.
As the resistive states of a resistive memory cell of a CBRAM and of a PCRAM memory differ by several orders of magnitude, considerable deviations may occur between the voltage actually applied to the memory cell and the desired read voltage, depending on the voltage source used. Reliable evaluation of the memory state, however, requires the application of a constant and reproducible read voltage to the memory cell. For example, a small resistance value of the memory cell may result in a breakdown of a voltage applied to the memory cell, thus disabling any current flow required for evaluation. In order to avoid such interference in the case of CBRAM or PCRAM memory chips, the voltage applied to the resistive memory cell and the reference cells is regulated to the predetermined read voltage by means of voltage regulation circuits. A voltage regulation circuit usually comprises a fed-back operational amplifier and a regulation transistor connected to an output of the operational amplifier, which requires considerably complex circuitry.
Instead of using a memory cell of a memory chip as binary coded memory cell for storing one bit and of merely switching the memory cell between two different resistive states (logical “0” and logical “1”), it is possible to operate a memory cell as a so-called multi level cell (MLC) for storing several bits by means of a larger number of memory states. Storing of 2-bit information, for example, is carried out with the aid of four distinguishable resistive states of a memory cell.
A multi level operating mode of memory cells is known for flash memories. For evaluating a memory state of a flash memory cell, a predetermined read voltage is applied to the flash memory cell or to its source/drain channel, respectively, and an electrical quantity is detected depending on an electrical current caused thereby. The electrical quantity is compared to reference quantities of an electrical current generated by the application of the predetermined read voltage to reference cells. Thereby, the reference cells comprise reference states with resistance values between the individual memory states of the flash memory cell to be read out. In a 2-bit operating mode, for example, three reference cells comprising different reference states are employed in order to determine a respective memory state of the flash memory cell out of four possible memory states. The setting of the predetermined read voltage at the flash memory cell to be evaluated and at the reference cells is carried out by means of transistors which are operated as source followers.
The possibility of a multi level operating mode is also given with respect to a CBRAM and a PCRAM memory chip since a resistive memory cell may be switched between a highly resistive memory state and several lowly resistive memory states. For evaluating the memory state of a resistive memory cell, the read-out concept known for flash memories cannot be used, however, since, contrary to flash memory cells, the resistive states of resistive memory cells are within a resistance range which comprises several orders of magnitude, as described above. Setting the read voltage by means of transistors operated as source followers would thus result in a read voltage drop in lowly resistive memory states, thus affecting an evaluation or rendering it impossible. Although such an impairment may be compensated by means of the above-described voltage stabilization or voltage regulation, respectively, the application of voltage regulation circuits for memory cells as well as for reference cells would, however, cause a relatively complex circuitry and thus a relatively high demand for space for a memory chip providing a multi level operating mode.